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january 2011 ? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan3268 ? rev. 1.0.1 1 fan3268 ?2a low-voltage pmos-nmos bridge driver fan3268 2a low-voltage pmos-nmos bridge driver features ? 4.5v to 18v operating range ? drives high-side pmos and low-side nmos in motor control or buck step-down applications ? inverting channel b biases high-side pmos device off (with internal 100k ? resistor) when v dd is below uvlo threshold ? ttl input thresholds ? 2.4a sink / 1.6a source at v out= 6v ? internal resistors turn driver off if no inputs ? millerdrive? technology ? 8-lead soic package ? rated from ?40c to +125c ambient applications ? motor control with pmos / nmos half-bridge configuration ? buck converters with high-side pmos device; 100% duty cycle operation possible ? logic-controlled load circuits with high-side pmos switch description the fan3268 dual 2a gate driver is optimized to drive a high-side p-channel mosfet and a low-side n-channel mosfet in motor control app lications operating from a voltage rail up to 18v. the driver has ttl input thresholds and provides buffer and level translation functions from logic inputs. in ternal circuitry provides an under-voltage lockout function that prevent s the output switching devices from operating if the v dd supply voltage is below the operat ing level. internal 100k ? resistors bias the non-in verting output low and the inverting output to v dd to keep the external mosfets off during startup intervals when logic control signals may not be present. the fan3268 driver incorporates millerdrive? architecture for the final output stage. this bipolar- mosfet combination provi des high current during the miller plateau stage of the mo sfet turn-on / turn-off process to minimize switching loss, while providing rail- to-rail voltage swing and reverse current capability. the fan3268 has two independent enable pins that default to on if not connect ed. if the enable pin for non- inverting channel a is pulled low, outa is forced low; if the enable pin for inverting channel b is pulled low, outb is forced high. if an input is left unconnected, internal resistors bias the i nputs such that the external mosfets are off. figure 1. typical motor drive application
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan3268 ? rev. 1.0.1 2 fan3268 ?2a low-voltage pmos-nmos bridge driver ordering information part number logic input threshold packing method fan3268tmx non-inverting channel and inverting channel + dual enables ttl 2,500 units on tape & reel package outline figure 2. pin configuration (top view) thermal characteristics (1) package ? jl (2) ? jt (3) ? ja (4) ? jb (5) ? jt (6) units 8-pin small outline integrated circuit (soic) 40 31 89 43 3 c/w notes: 1. estimates derived from thermal simulati on; actual values depend on the application. 2. theta_jl ( ? jl ): thermal resistance between the semi conductor junction and the bottom surfac e of all the leads (including any thermal pad) that are typically soldered to a pcb. 3. theta_jt ( ? jt ): thermal resistance between the se miconductor junction and the top surfac e of the package, assuming it is held at a uniform temperature by a top-side heatsink. 4. theta_ja ( ja ): thermal resistance between junction and ambient, dependent on the pcb design, heat sinking, and airflow. the value given is for natural convection with no heatsink us ing a 2s2p board, as specifi ed in jedec standards jesd51-2, jesd51-5, and jesd51-7, as appropriate. 5. psi_jb ( ? jb ): thermal characterization parameter providing co rrelation between semiconductor junction temperature and an application circuit board reference point fo r the thermal environment defined in note 4. for the soic-8 package, the board reference is defined as the pc b copper adjacent to pin 6. 6. psi_jt ( ? jt ): thermal characterization parameter providing corre lation between the semiconducto r junction temperature and the center of the top of the package for the thermal environment defined in note 4.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan3268 ? rev. 1.0.1 3 fan3268 ?2a low-voltage pmos-nmos bridge driver pin definitions pin# name description 1 ena enable input for channel a . pull pin low to inhibit driver a. ena has ttl thresholds. 8 enb enable input for channel b . pull pin low to inhibit driver b. enb has ttl thresholds. 3 gnd ground . common ground reference for input and output circuits. 2 ina input to channel a . 4 inb input to channel b . 7 outa gate drive output a : held low unless required input(s) are present and v dd is above the uvlo threshold. 5 outb gate drive output b (inverted from the input): held high unless required input is present and v dd is above uvlo threshold. 6 vdd supply voltage . provides power to the ic. output logic fan3268 (channel a) fan3268 (channel b) ena ina outa enb inb outb 0 0 (7) 0 0 0 (7) 1 0 1 0 0 1 1 1 (7) 0 (7) 0 1 (7) 0 (7) 1 1 (7) 1 1 1 (7) 1 0 note: 7. default input signal if no external connection is made.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan3268 ? rev. 1.0.1 4 fan3268 ?2a low-voltage pmos-nmos bridge driver block diagram 6 vdd 7 v dd_ok 5 ina 2 100k ? ena 1 gnd 3 vdd uvlo 100k ? 8 vdd enb inb 4 outa 100k ? 100k ? 100k ? outb 100k ? figure 3. block diagram
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan3268 ? rev. 1.0.1 5 fan3268 ?2a low-voltage pmos-nmos bridge driver absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the devic e may not function or be operable above the recommended operating c onditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stre sses above the recommended operating conditi ons may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v dd vdd to pgnd -0.3 20.0 v v en ena, enb to gnd gnd - 0.3 v dd + 0.3 v v in ina, inb to gnd gnd - 0.3 v dd + 0.3 v v out outa, outb to gnd gnd - 0.3 v dd + 0.3 v t l lead soldering temperature (10 seconds) +260 oc t j junction temperature -55 +150 oc t stg storage temperature -65 +150 oc esd electrostatic discharge protection level human body model, jedec jesd22-a114 3.5 kv charged device model, jedec jesd22-c101 2 kv recommended operating conditions the recommended operating conditions table defines the conditions for actual device oper ation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specificat ions. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. max. unit v dd supply voltage range 4.5 18.0 v v en enable voltage (ena, enb) 0 v dd v v in input voltage (ina, inb) 0 v dd v t a operating ambient te mperature -40 +125 oc electrical characteristics unless otherwise noted, v dd =12v and t j =-40c to +125c. currents are defi ned as positive into the device and negative out of the device. symbol parameter conditions min. typ. max. unit supply v dd operating range 4.5 18.0 v i dd supply current inputs / en not connected 0.75 1.20 ma v on turn-on voltage ina=ena=v dd , inb=enb=0v 3.5 3.9 4.3 v v off turn-off voltage ina=ena=v dd , inb=enb=0v 3.3 3.7 4.1 v input (8) v il inx logic low threshold 0.8 1.2 v v ih inx logic high threshold 1.6 2.0 v v hys logic hysteresis vo ltage 0.2 0.4 0.8 v
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan3268 ? rev. 1.0.1 6 fan3268 ?2a low-voltage pmos-nmos bridge driver electrical characteristics (continued) unless otherwise noted, v dd =12v and t j =-40c to +125c. currents are defi ned as positive into the device and negative out of the device. enable v enl enable logic low threshold en from 5v to 0v 0.8 1.2 v v enh enable logic high threshold en from 0v to 5v 1.6 2.0 v v hys logic hysteresis voltage (9) 0.4 v r pu enable pull-up resistance (9) 100 k ? output i sink out current, mid-voltage, sinking (9) out at v dd /2, c load =0.1f, f=1khz 2.4 a i source out current, mid-voltage, sourcing (9) out at v dd /2, c load =0.1f, f=1khz -1.6 a i pk_sink out current, peak, sinking (9) c load =0.1f, f=1khz 3 a i pk_source out current, peak, sourcing (9) c load =0.1f, f=1khz -3 a t rise output rise time (10) c load =1000pf 12 22 ns t fall output fall time (10) c load =1000pf 9 17 ns t d1 propagation delay (10) 0 - 5v in , 1v/ns slew rate 7 14 25 ns t d2 propagation delay (10) 0 - 5v in , 1v/ns slew rate 10 19 34 ns notes: 8. en inputs have ttl thresholds ; refer to the enable section. 9. not tested in production. 10. see the timing diagrams of figure 4 and figure 5 . timing diagrams figure 4. non-inverting figure 5. inverting
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan3268 ? rev. 1.0.1 7 fan3268 ?2a low-voltage pmos-nmos bridge driver typical performance characteristics typical characteristics are provided at t a =25c and v dd =12v unless otherwise noted. figure 6. i dd (static) vs. supply voltage (11) figure 7. i dd (no-load) vs. frequency figure 8. i dd (1nf load) vs. frequency figure 9. i dd (static) vs. temperature (11) figure 10. input thresholds vs. supply voltage figure 11. input thresholds vs. temperature
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan3268 ? rev. 1.0.1 8 fan3268 ?2a low-voltage pmos-nmos bridge driver typical performance characteristics typical characteristics are provided at t a =25c and v dd =12v unless otherwise noted. figure 12. uvlo threshold vs. temperature figure 13. propagation delays vs. supply voltage figure 14. propagation delays vs. supply voltage figure 15. propagation delays vs. temperature figure 16. propagation delays vs. temperature
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan3268 ? rev. 1.0.1 9 fan3268 ?2a low-voltage pmos-nmos bridge driver typical performance characteristics typical characteristics are provided at t a =25c and v dd =12v unless otherwise noted. figure 17. fall time vs. supply voltage figure 18. rise time vs. supply voltage figure 19. rise and fall times vs. temperature figure 20. rise/fall waveforms with 1nf load figure 21. rise/fall waveforms with 10nf load
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan3268 ? rev. 1.0.1 10 fan3268 ?2a low-voltage pmos-nmos bridge driver typical performance characteristics typical characteristics are provided at t a =25c and v dd =12v unless otherwise noted. figure 22. quasi-static source current with v dd =12v figure 23. quasi-static sink current with v dd =12v figure 24. quasi-static source current with v dd =8v figure 25. quasi-static sink current with v dd =8v note: 11. for any inverting inputs pulled low, non-inverting inputs pulled high, or output s driven high, static i dd increases by the current flowing through the corre sponding pull-up/down resistor shown in the block diagram in figure 3. test circuit figure 26. quasi-static i out / v out test circuit
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan3268 ? rev. 1.0.1 11 fan3268 ?2a low-voltage pmos-nmos bridge driver applications information input thresholds the fan3268 driver has ttl input thresholds and provides buffer and level translation functions from logic inputs. the input threshol ds meet industry-standard ttl-logic thresholds, independent of the v dd voltage, and there is a hysteresis vo ltage of approximately 0.4v. these levels permit the inputs to be driven from a range of input logic signal levels fo r which a voltage over 2v is considered logic high. the driving signal for the ttl inputs should have fast rising and falling edges with a slew rate of 6v/s or faster, so a rise time from 0 to 3.3v should be 550ns or less. with reduced slew rate, circuit noise could cause the driver input voltage to exceed the hysteresis voltage and retrigger the driver input, causing erratic operation. static supply current in the i dd (static) typical performance characteristics (see figure 6) , the curve is produced with all inputs / enables floating (out is low) and indicates the lowest static i dd current for the tested c onfiguration. for other states, additional current flows through the 100k ? resistors on the inputs and out puts shown in the block diagram ( see figure 3) . in these cases, the actual static i dd current is the value obtai ned from the curves plus this additional current. millerdrive? gate drive technology fan3268 gate drivers incor porate the millerdrive? architecture shown in 0. for the output stage, a combination of bipolar and mos devices provide large currents over a wide r ange of supply voltage and temperature variations. the bipolar devices carry the bulk of the current as out swings between one and two thirds v dd and the mos devices pu ll the output to the high or low rail. the purpose of the millerdrive ? architecture is to speed up switching by providing hi gh current during the miller plateau region when the gate- drain capacitance of the mosfet is being charged or discharged as part of the turn-on / turn-off process. for applications with zero voltage switching during the mosfet turn-on or turn-off interval, the driver supplies high peak current for fast switching even though the miller plateau is not present. th is situation often occurs in synchronous rectifier app lications because the body diode is generally conducting before the mosfet is switched on. the output pin slew rate is determined by v dd voltage and the load on the output. it is not user adjustable, but a series resistor can be added if a slower rise or fall time at the mosfet gate is needed. figure 27. millerdrive? output architecture under-voltage lockout internal circuitry provides an under-voltage lockout function that prevent s the output switching devices from operating if the v dd supply voltage is below the operating level. when v dd is rising, but below the 3.9v operational level, internal 100k ? resistors bias the non- inverting output low and t he inverting output to v dd to keep the external mosfets o ff during startup intervals when logic control signals may not be present. after the part is active, the supply vo ltage must drop 0.2v before the part shuts down. this hysteresis helps prevent chatter when low v dd supply voltages have noise from the power switching. v dd bypass capacitor guidelines to enable this ic to turn a device on quickly, a local high-frequency bypass capacitor c byp with low esr and esl should be connected between the vdd and gnd pins with minimal trace lengt h. this capacitor is in addition to bulk electrolytic capacitance of 10f to 47f commonly found on driver and controller bias circuits. a typical criterion for choosing the value of c byp is to keep the ripple voltage on the v dd supply to 5%. this is often achieved with a value 20 times the equivalent load capacitance c eqv , defined here as q gate /v dd . ceramic capacitors of 0.1f to 1f or larger are common choices, as are dielectrics, such as x5r and x7r, with good temperatur e characteristics and high pulse current capability. if circuit noise affects normal operation, the value of c byp may be increased to 50-100 times the c eqv or c byp may be split into two capacit ors. one should be a larger value, based on equivalent load capacitance, and the other a smaller value, such as 1-10nf mounted closest to the vdd and gnd pins to carry the higher frequency components of the current pul ses. the bypass capacitor must provide the pulsed current from both of the driver channels and, if the dr ivers are switching simultaneously, the combi ned peak current sourced from the c byp would be twice as large as when a single channel is switching.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan3268 ? rev. 1.0.1 12 fan3268 ?2a low-voltage pmos-nmos bridge driver layout and connection guidelines the fan3268 gate driver in corporates fast-reacting input circuits, short pr opagation delays, and powerful output stages capable of deliv ering current peaks over 2a to facilitate voltage trans ition times from under 10ns to over 150ns. the following layout and connection guidelines are strongly recommended: ? keep high-current output and power ground paths separate from l ogic and enable input signals and signal ground paths. this is especially critical when dealing with ttl-level logic thresholds at driver inputs and enable pins. ? keep the driver as close to the load as possible to minimize the length of high-current traces. this reduces the series induc tance to improve high- speed switching, while r educing the loop area that can radiate emi to the driver inputs and surrounding circuitry. ? if the inputs to a channel are not externally connected, the internal 100k ? resistors indicated on block diagrams command a low output (channel a) or a high output (channel b). in noisy environments, it may be necessary to tie inputs or enables of an unused channel to vdd or gnd using short traces to prevent noise from causing spurious output switching. ? many high-speed power circuits can be susceptible to noise injected from t heir own output or other external sources, possibly causing output re- triggering. these effect s can be obvious if the circuit is tested in breadboard or non-optimal circuit layouts with long input, enable, or output leads. for best results, make connections to all pins as short and direct as possible. ? the turn-on and turn-off current paths should be minimized. operational waveforms figure 28 shows startup waveforms for non-inverting channel a. at power-up, the driver output for channel a remains low until the v dd voltage reaches the uvlo turn- on threshold, then outa operates in-phase with ina. figure 28. non-inverting startup waveforms figure 29 illustrates startup waveforms for inverting channel b. at power-up, the driver output for channel b is tied to v dd through an internal 100k ? resistor until the v dd voltage reaches the uvlo turn-on threshold, then outb operates out of phase with inb. figure 29. inverting startup waveforms
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan3268 ? rev. 1.0.1 13 fan3268 ?2a low-voltage pmos-nmos bridge driver thermal guidelines gate drivers used to switch mosfets and igbts at high frequencies can dissipate significant amounts of power. it is important to determine the driver power dissipation and the resulting j unction temperature in the application to ensure that t he part is operating within acceptable temperature limits. the total power dissipation in a gate driver is the sum of two components, p gate and p dynamic : p total =p gate + p dynamic (1) gate driving loss: the most significant power loss results from supplying gat e current (charge per unit time) to switch the load mosfet on and off at the switching frequency. the power dissipation that results from driving a mo sfet at a specified gate- source voltage, v gs , with gate charge, q g , at switching frequency, f sw , is determined by: p gate =q g ? v gs ? f sw ? n (2) where n is the number of driver channels in use (1 or 2). dynamic pre-drive / shoot-through current: a power loss resulting from internal current consumption under dynamic operating conditions, including pin pull-up / pull-down resistors, can be obtained using the ?i dd (no-load) vs. frequency? graphs in typical performance characteristics to determine the current i dynamic drawn from v dd under actual operating conditions: p dynamic =i dynamic ? v dd ? n (3) once the power dissipated in the driver is determined, the driver junction rise with respect to circuit board can be evaluated using the fo llowing thermal equation, assuming ? jb was determined for a similar thermal design (heat sinking and air flow): t j =p total ? ? jb + t b (4) where: t j =driver junction temperature ? jb =(psi) thermal characterization parameter relating temperature rise to total power dissipation t b =board temperature in location defined in note 1 under thermal resistance table. as an example of a power dissipation calculation, consider an application driving two mosfets with a gate charge of 60nc with v gs =v dd =7v. at a switching frequency of 500khz, the total power dissipation is: p gate =60nc ? 7v ? 500khz ? 2=0.42w (5) p dynamic =3ma ? 7v ? 2=0.042w (6) p total =0.46w (7) the soic-8 has a junction-to-board thermal characterization parameter of ? jb =43c/w. in a system application, the localized te mperature around the device is a function of the layout and construction of the pcb along with airflow across the surfaces. to ensure reliable operation, the maximu m junction temperature of the device must be prev ented from exceeding the maximum rating of 150c; with 80% derating, t j would be limited to 120c. rearr anging equation 4 determines the board temperature required to maintain the junction temperature below 120c: t b =t j - p total ? ? jb (8) t b =120c ? 0.46w ? 43c/w=100c (9)
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan3268 ? rev. 1.0.1 14 fan3268 ?2a low-voltage pmos-nmos bridge driver table 1. related products part number type gate drive (12) (sink/src) input threshold logic package fan3111c single 1a +1.1a / -0.9a cmos single channel of dual-input/single-output sot23-5, mlp6 fan3111e single 1a +1.1a / -0.9a external (13) single non-inverting channel with ex ternal reference sot23-5, mlp6 fan3100c single 2a +2.5a / -1.8a cmos single c hannel of two-input/one-output sot23-5, mlp6 FAN3100T single 2a +2.5a / -1.8a ttl single c hannel of two-input/one-output sot23-5, mlp6 fan3226c dual 2a +2.4a / -1.6a cmos dual inverting channels + dual enable soic8, mlp8 fan3226t dual 2a +2.4a / -1.6a ttl dual in verting channels + dual enable soic8, mlp8 fan3227c dual 2a +2.4a / -1.6a cmos dual n on-inverting channels + dual enable soic8, mlp8 fan3227t dual 2a +2.4a / -1.6a ttl dual non- inverting channels + dual enable soic8, mlp8 fan3228c dual 2a +2.4a / -1.6a cmos dual channels of two-input/one-output, pin config.1 soic8, mlp8 fan3228t dual 2a +2.4a / -1.6a ttl dual channels of two-input/one-output, pin config.1 soic8, mlp8 fan3229c dual 2a +2.4a / -1.6a cmos dual channels of two-input/one-output, pin config.2 soic8, mlp8 fan3229t dual 2a +2.4a / -1.6a ttl dual channels of two-input/one-output, pin config.2 soic8, mlp8 fan3268t dual 2a +2.4a / -1.6a ttl non-inverting channel (nmos) and inverting channel (pmos) + dual enables soic8 fan3223c dual 4a +4.3a / -2.8a cmos dual inverting channels + dual enable soic8, mlp8 fan3223t dual 4a +4.3a / -2.8a ttl dual in verting channels + dual enable soic8, mlp8 fan3224c dual 4a +4.3a / -2.8a cmos dual n on-inverting channels + dual enable soic8, mlp8 fan3224t dual 4a +4.3a / -2.8a ttl dual non- inverting channels + dual enable soic8, mlp8 fan3225c dual 4a +4.3a / -2.8a cmos dual channels of two-input/one-output soic8, mlp8 fan3225t dual 4a +4.3a / -2.8a ttl dual channels of two-input/one-output soic8, mlp8 fan3121c single 9a +9.7a / -7.1a cmos singl e inverting channel + enable soic8, mlp8 fan3121t single 9a +9.7a / -7.1a ttl singl e inverting channel + enable soic8, mlp8 fan3122t single 9a +9.7a / -7.1a cmos single non-inverting channel + enable soic8, mlp8 fan3122c single 9a +9.7a / -7.1a ttl single non-inverting channel + enable soic8, mlp8 notes: 12. typical currents with out at 6v and v dd= 12v. 13. thresholds proportional to an exte rnally supplied reference voltage.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan3268 ? rev. 1.0.1 15 fan3268 ?2a low-voltage pmos-nmos bridge driver physical dimensions 8 0 see detail a notes: unless otherwise specified a) this package conforms to jedec ms-012, variation aa, issue c, b) all dimensions are in millimeters. c) dimensions do not include mold flash or burrs. d) landpattern standard: soic127p600x175-8m. e) drawing filename: m08arev13 land pattern recommendation seating plane 0.10 c c gage plane x 45 detail a scale: 2:1 pin one indicator 4 8 1 c m ba 0.25 b 5 a 5.60 0.65 1.75 1.27 6.20 5.80 3.81 4.00 3.80 5.00 4.80 (0.33) 1.27 0.51 0.33 0.25 0.10 1.75 max 0.25 0.19 0.36 0.50 0.25 r0.10 r0.10 0.90 0.406 (1.04) option a - bevel edge option b - no bevel edge figure 30. 8-lead small outline integrated circuit (soic) package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan3268 ? rev. 1.0.1 16 fan3268 ?2a low-voltage pmos-nmos bridge driver

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